1. Field of the Disclosure
The present disclosure relates to a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), and more particularly, to an SAR ADC which can maintain an optimal operating time for resolution and improve stability by improving a response time, and an analog-to-digital conversion method using the same.
2. Discussion of the Related Art
An ADC is a device for converting an analog signal into a digital code. The ADC samples the analog signal and converts the sampled analog signal into a digital code or digital signal corresponding to magnitude of the sampled analog signal. Among ADCs, an SAR ADC including an SAR combines digital codes while sequentially increasing or decreasing from a significant bit and compares the combined digital code with an analog signal to approximate to the analog signal.
A typical SAR ADC includes an N-bit (where N is an integer equal to or greater than 1) Digital-to-Analog Converter (DAC) and a comparator. The N-bit DAC converts an N-bit digital code into a corresponding analog voltage. The comparator compares the analog voltage generated from the N-bit DAC with an input analog signal. If the input analog signal is greater than the analog voltage, the comparator generates a high level signal, i.e. a signal having a logic value of 1. If the analog voltage is greater than or equal to the input analog signal, the comparator generates a low level signal, i.e. a signal having a logic value of 0.
When setting a Most Significant Bit (MSB) of the digital code input to the N-bit DAC to a logic value of 1, and comparing the input analog signal with the analog voltage generated from the N-bit DAC, an MSB of an N-bit digital code can be determined. Next, the above-described comparison process is repeated while sequentially changing a subsequent bit of the digital code input to the N-bit DAC to determine the N-bit digital code corresponding to the analog signal.
However, such a conventional SAR ADC includes a start stage and an inverting gate for resetting an SR flip-flop generating a digital signal of MSB. A start signal START is input to the start stage, and then a phase of the start signal START is inverted in the inversion gate via the start stage and thus inversion gate generates a reset signal RESET. When the reset signal RESET is input to the SR flip-flop, the SR flip-flop generates the digital signal of MSB. In this case, since the digital signal of the MSB has a 2-phase difference with the start signal START as shown in FIG. 1, an operating time is increased. Accordingly, it is difficult to operate the SAR during a time optimized for resolution, and in order to achieve the same operating time suitable for resolution, the SAR encounters problems such as fast supply of a clock period input to the SAR.
Furthermore, the conventional DAC is comprised of binary weighted capacitors as shown in FIG. 2. The DAC comprised of the binary weighted capacitors has linearity higher than a resistor and facilitates low-power design. However, as resolution is increased, a ratio of capacitors having the largest size to capacitors having the smallest size is abruptly increased. For example, in the case of an 8-bit DAC, the size of a capacitor corresponding to the MSB is 128 times a minimum capacitor size. If a unit capacitor is used for matching characteristics, 256 capacitors are needed. Thus, if the size of a capacitor determined in consideration of matching is very large, a total area of the DAC is increased, thereby deteriorating integration and complicating a circuit.